As is well known, a solid state drive (hereinafter, SSD) is a data storage drive that uses NAND flash memories to store data. Solid state drive with NAND flash memories is a non-volatile memory device. After being written to the non-volatile memory, the data are retained in the solid state drive even if power supply system is off.
It is well known that the flash memory includes a memory cell array composed of plural memory cells. Each memory cell in the flash memory includes a floating gate transistor.
In a program cycle, hot carriers, such as electronics, are injected to a floating gate of the floating gate transistor. With the injected hot carriers, the threshold voltage of the floating gate transistor will change and various storage states are accordingly generated. Different storage states are corresponding to various distributions of threshold voltage.
FIG. 1 is a schematic diagram illustrating storage state versus threshold voltage distribution of the flash memory. Take a flash memory with single-level cell (hereinafter, SLC) as an example, a memory cell may have two storage states, that is, a first storage state (E) and a second storage state (A).
By calculating the threshold voltage of all memory cells, it is found that distributions of the threshold voltages of the memory cells at the first storage state (E) are close to a first threshold voltage level VTHE, and distributions of the threshold voltages of the memory cells at the second storage state (A) are close to a second threshold voltage level VTHA. Thus, a slice voltage (Vs) can be utilized to determine storage states of most of the memory cells. That is to say, the memory cells with threshold voltage less than the slice voltage are determined to be at the first storage state (E), and the memory cells with threshold voltage greater than the slice voltage are determined to be at the second storage state (A).
However, when threshold voltages of some memory cells at the first storage state (E) are greater than the slice voltage (Vs), these memory cells will be mistakenly determined as being at the second storage state (A). Similarly, when threshold voltages of some memory cells at the second storage state (A) are less than the slice voltage (Vs), these memory cells will be mistakenly determined as being at the first storage state (E).
Similarly, storage states of a flash memory with multi-level cell (hereinafter, MLC) may be mistakenly determined. In such case, the solid state drive needs a mechanism to correct the error.
FIG. 2 is a schematic diagram illustrating a conventional solid state drive. The solid state drive 10 includes a processing circuit 101, a buffer 107 and a flash memory 105. Between the processing circuit 101 and the host 12, an external bus 14 is used to transmit command and data. The external bus 14 may be a USB bus, an IEEE 1394 bus or a SATA bus etc.
When the host 12 writes data to the flash memory 105, the host 12 will transmit a write command and write data to the solid state drive 10. Meanwhile, the ECC controller 103 in the processing circuit 101 will generate an error check and correction (hereinafter, ECC) code corresponding to the write data. Afterward, the processing circuit 101 will write both the write data and the ECC code to the flash memory 105.
When the host 12 needs to read the data stored in the flash memory 105, the host 12 will generate a read command to the solid state drive 10. After retrieving a read data and its corresponding ECC code from the flash memory 105, the processing circuit 101 temporarily stores the read data and the ECC code to the buffer 107. Then, the ECC controller 103 will verify the read data according to the ECC code. After the ECC controller 103 confirms correctness of the read data, the processing circuit 101 will output the read data to the host 12.
In general, a conventional ECC controller 103 corrects read data by utilizing only one ECC algorithm. When the ECC controller 103 confirms the error of the read data is uncorrectable, the processing circuit 101 cannot output correct read data. Meanwhile, the processing circuit 101 will mark a position of the incorrect read data in the flash memory 105. Later, the processing circuit 101 will retry to correct the incorrect read data when the solid state drive 10 is in a standby mode.
Therefore, in a case that the error of the read data is uncorrectable, the processing circuit 101 cannot recover the read data in real time but has to wait until the standby mode to retry to correct the error. An attempt of correcting the error of the read data in real time results in dramatic drop of data throughput of the solid state drive 10 and seriously affects performance of the solid state drive 10.